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Dr Jose Nunez-Yanez

Dr Jose Nunez-Yanez

Dr Jose Nunez-Yanez
BSc, MSc, PhD(Lough)

Reader in Adaptive and Energy Efficient Computing

Office 5.15 MVB
Merchant Venturers Building,
Woodland Road, Clifton BS8 1UB
(See a map)

+44 (0) 117 331 5128

Summary

I am an expert in adaptive and energy efficient computing as evidenced by my research grants as principal investigator that result in technology used at an international scale, my publications as first author in high-quality journals, conference publications that receive best papers awards and my industrially sponsored research with leading multinational companies in the field of microelectronics. One of my objectives since joining Bristol has been to have a strong industrial relevance in both teaching and research.  I have followed a hands-on approach towards research and aimed at conducting part of my research within industry to follow best industrial practices and methods.  The research at ST,Italy during my Marie Curie fellowship in reconfigurable processors and interconnect lead to further funding from EPSRC (PI £500K) together with Manchester University following my progression to SL in 2007. Key components of this work were made publicly available in open-source format to increase the dissemination of the research and strengthen the impact of publications.  The work done with the Innovation Triangle Initiative created by European Space Agency (PI £50K) during 2010 build on previous EPSRC research and resulted in a family of high-performance reconfigurable compressors that can adapt in real-time to the data type being compressed. Currently, this work is being used in different industrial and academic projects around the world as a reference system.  Energy efficiency is one of mine main areas of interest and key in the semiconductor. In this topic I obtained a Royal Society fellowship working at ARM, Cambridge (a world leader in microprocessor intellectual property) for one year. The work done at ARM investigated a new modelling approach using high-level information to understand how power and energy is used in modern complex system-on-chips.  This work was published in several journals and conferences and it is currently one of the most downloaded papers in the Elsevier Microprocessors and Microsystems journal. ARM is using the results in the EuroCloud project and in their own system simulator called Gem5. In 2013 I obtained an industrial CASE award (£100K) funded by ARM and EPSRC to investigate how the techniques created during my fellowship can be used in ARM big.LITTLE heterogeneous processors that combined processing cores of different complexity.   Also at the end of 2013 I obtained as PI an EPSRC grant worth £900K in the area of energy proportional and adaptive computing working with programming experts from QuB with Bristol as lead institution and £75K from DSTL to explore how this technology can be used in military signal processing applications.  Examples of CI include the collaboration in the EU funded ENTRA project (£700K) and work with the TSB, DSTL and MoD in energy-efficient signal processing (£150K). In 2014 I have aimed at increasing the impact of my research and establish a research collaboration with defense company Qioptiq to create the first low-power and low-cost data fusion system for man portable applications. The first work package sponsored by the company (£5K) will be delivered in December and further work is expected. A similar collaboration has been built with University of Oxford and the SKA (Square Kilometer Array) multinational project.

Biography

Jose Nunez-Yanez is a senior lecturer in digital systems at the University of Bristol and part of the microelectronics group. He holds a PhD in hardware-based parallel data compression from the University of Loughborough, UK with three patents awarded on the topic of high-speed parallel data compression. His main area of expertise is in the design of reconfigurable architectures for signal processing with a focus on run-time adaptation, parallelism and energy-efficiency. In 2006 he was a Marie Curie research fellow at ST Microelectronics, Milan, Italy. He investigated how to achieve an optimal coupling between a RISC processor and a dynamically reconfigurable fabric to perform automatic extensions to the standard instruction set architecture of the processor [1]. He collaborated with the European Space Agency (ESA) investigating run-time hardware adaptation to support optimal statistical compression of different data types with support by EPSRC under grant EP/D011639/1 [2]. This work was further funded by ESA through the Innovation Triangle Initiative to show the benefits of the technology in Space reducing the power and energy needs of on-board data processing systems .  He is active in the areas of power efficient computing [3] with the EPSRC ENPOWER and FP7 ENTRA projects, signal processing [4] and on-chip communication architectures [5]. In 2011 he was a royal society research fellow at ARM Ltd, Cambridge, UK investigating high-level modelling of the energy consumption of heterogeneous many-core systems [6]. This work advanced previous work that had focus on the microprocessor to add mathematical models for other components such as memory and display sub-systems. He has authored over 100 journal and conference publications.

Teaching

Second year Digital Systems

Third year Embedded and Real-Time Systems

MSc Advanced DSP&FPGA Implementation

Keywords

  • Reconfigurable computing
  • Video coding
  • Multiprocessors
  • Lossless data compression
  • Energy efficient computing

Recent publications

View complete publications list in the University of Bristol publications system

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