Unit information: Design Verification (Teaching Unit) in 2020/21

Unit name	Design Verification (Teaching Unit)
Unit code	COMS30026
Credit points	0
Level of study	H/6
Teaching block(s)	Teaching Block 1 (weeks 1 - 12)
Unit director	Professor. Eder
Open unit status	Not open
Pre-requisites	COMS10016 Imperative and Functional Programming and COMS10017 Object-Oriented Programming and Algorithms I or equivalent. COMS20008 Computer Systems A or equivalent. Strong programming skills, software engineering skills and a basic understanding of computer architecture.
Co-requisites	EITHER Assessment Units COMS30024 Design Verification (Examination assessment, 10 credits) OR COMS30025 Design Verification (Coursework assessment, 20 credits). Please note: COMS30026 is the Teaching Unit for the Design Verification option. Single Honours Computer Science students can choose to be assessed by either examination (10 credits, COMS30024) or coursework (20 credits, COMS30025) by selecting the appropriate co-requisite assessment unit. Any other students that are permitted to take the Design Verification option are assessed by examination (10 credits) and should be enrolled on the co-requisite exam assessment unit (COMS30024).
School/department	School of Computer Science
Faculty	Faculty of Engineering

Description including Unit Aims

This unit introduces students to theoretical and practical aspects of design verification with examples from computer architecture and processor design. It starts with an overview of various verification techniques and explores their limits. We investigate two major topics: Simulation-based Testing (dynamic verification) and Property Checking (static verification). Simulation-based Testing includes the use of simulators, testbench components, collecting and measuring coverage, as well as assertion-based verification and requirements formalization. Property Checking investigates formal model checking techniques and features of state-of-the-art tools, the advantages and limitations of formal verification techniques and how simulation-based techniques can complement formal verification. The course also offers lectures on design and verification flow, including how to write a verification plan.

Unit Aim: This unit familiarises students with the methods and techniques used in the design verification process, and gives them the technical background plus some of the practical skills (if assessed by coursework) expected from a design verification engineer.

Intended Learning Outcomes

General ILOs

On successful completion of this unit, students will be able to:

1. Appreciate the process of design verification, its complexities and limits.
2. Understand a variety of state-of-the-art verification techniques, including test-based and formal methods, their foundations, practical use and limits.
3. Carry out functional verification and determine its effectiveness.
4. Set verification goals and select suitable verification methods and techniques to achieve these.

In addition to the General ILOs above, when assessed by examination, students will be able to:

1. Compile a verification plan.

In addition to the General ILOs above, when assessed by coursework, students will be able to:

On successful completion of this unit, students will be able to:

1. Compile a verification plan and realize this plan by implementing a verification environment to as part of a small verification project.
2. Organise resources to be used for a verification project and monitor progress.

Teaching Information

Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions and self-directed exercises.

Teaching will take place over Weeks 1-7, with coursework support in weeks 8-10 and for students assessed by examination, consolidation and revision sessions in Weeks 11 and 12.

Assessment Information

Examination details

January timed assessment (10 credits).

OR

Coursework details

Coursework, to be completed over weeks 8-10. (100%, 20 credits)

Reading and References

Bergeron, J., Writing Testbenches: Functional Verification of HDL Models, Second Edition (Kluwer Academic Publishers, 2003) ISBN: 978-1461503026