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| Unit name |
VLSI Design M |
| Unit code |
EENGM4050 |
| Credit points |
10 |
| Level of study |
M/7
|
| Teaching block(s) |
Teaching Block 2 (weeks 13 - 24)
|
| Unit director |
Professor. Dinesh Pamunuwa |
| Open unit status |
Not open |
| Pre-requisites |
EENG20400 or equivalent
|
| Co-requisites |
None
|
| School/department |
School of Electrical, Electronic and Mechanical Engineering |
| Faculty |
Faculty of Engineering |
Description including Unit Aims
In this unit, VLSI design methodologies will be introduced. Transistor level implementations of basic logic gates will be covered. Physical layout of digital circuits will be considered. Techniques for designing high-speed, low-power and easily testable circuits will be presented. The students will make extensive use of industry standard CAD tools for integrated circuit design, simulation and layout verification.
VLSI Design
- Introduction to VLSI design methodology
- Transistor level design for static CMOS logic gates
- Review of MOS transistor theory and CMOS fabrication process
- Physical design: drawing conventions, design rules, layout, floorplanning, verification (DRC and LVS)
- Static load MOS inverters
- Circuit characterization and performance estimation: resistance, oxide and junction capacitance, layout of resistor and capacitor
- ‘Latch-up’ and prevention techniques
- Switching characteristics of MOS inverters: calculation of delay times, power dissipation
- Sequential CMOS logic gate design
- Design for testability: scan-path testing, boundary scan testing, built-in self test
- Low power circuit design: the importance of low power design, origin of power dissipation in VLSI circuits, algorithm, architecture, circuit and device level power optimisation
- Asynchronous design: the difference between synchronous and asynchronous design, 2- and 4- phase handshake protocol, data convention, delay model, event logic, micropipeline, GALS
Laboratory
- Students undertake two, 3 week, introductory VLSI exercises (schematic and layout design) to become familiar with Cadence design tools. In addition, students undertake a 5 week project to design a complex system.
- The 2nd introductory exercise and the design project are significantly more demanding than those associated with the EENG34050 VLSI unit.
- All coursework exercises are carried out by students in groups of 2.
Intended Learning Outcomes
Having completed this unit, students will be:
- Aware of the state-of-the-art CAD tools for transistor-level design of VLSI systems
- Capable of designing VLSI circuits
- Familiar with the physical layout of digital circuits.
- Aware of techniques for low-power and testable VLSI design
Teaching Information
Combination of lectures and laboratory sessions
Assessment Information
Reading and References
Kang, S. & Leblebici, Y, CMOS Digital Integrated Circuits, McGraw-Hill, 2003, ISBN 0072460539
