| Unit name | Advanced DSP & FPGA Implementation |
|---|---|
| Unit code | EENGM4120 |
| Credit points | 10 |
| Level of study | M/7 |
| Teaching block(s) |
Teaching Block 2 (weeks 13 - 24) |
| Unit director | Dr. Nunez-Yanez |
| Open unit status | Not open |
| Pre-requisites |
None |
| Co-requisites |
None |
| School/department | School of Electrical, Electronic and Mechanical Engineering |
| Faculty | Faculty of Engineering |
FPGA: This module extends the knowledge in digital systems with advance topics in the emergent area of reconfigurable computing and FPGA design. The course will cover state-of-the-art features available in modern FPGAs exploring their fine-grained internal architecture and embedded macro blocks such as DSP slices and hardwired processors. SystemC (a C++ class library) will be presented as design language alternative to traditional RTL design (VHDL, Verilog). High level synthesis tools will be used to map compute intensive kernels in signal processing applications from a generic DSP core to the FPGA device and the performance advantages will be evaluated. DSP: This module extends knowledge of signal processing techniques and gives students practical experience of using the state-of-the-art DSPs. The course covers generic techniques for developing design solutions for all DSP devices as well as focussing specifically on the TMS320C6000 DSP processor which is the flagship of Texas Instruments DSPs and also the Davinci DSP processor which is a system on chip with a C6000 DSP and an Arm Processor. It also covers the use of operating systems. This module provides practical experience.
Project Phase
The project contains a research or investigative element which allows you to demonstrate individual talent and intellectual ability. It attempts to mirror a research and/or development project of the type you might encounter upon graduation and as such contains elements of project planning and budgetary control. The project report also provides an opportunity for you to demonstrate report structuring and writing skills.
Teaching takes place over two Semesters, the first lasting for weeks 1-12 and the second for weeks 13-24. Exams normally commence in week 25 and last for approximately three weeks. The remainder of the programme is then dedicated to full-time work on the research project.
Taught phase
The taught units and their associated assessments (including examinations) occur in the first 35 weeks and the research project runs full-time during the latter 15 weeks of the programme. The taught material is presented over 2 Semesters, each 12 weeks in duration; excluding the Christmas and Easter vacations of 8 weeks in total. Further, the examinations are held May/June each year over a 3 week period. During the second Semester you will commence the background reading phase of your research project. The taught material is arranged in units extending over a 12-week period (a Semester), typically with 2 lectures per week, each of 50 minutes duration.
The Laboratory
Laboratory activities are scheduled for two afternoons a week during the first two terms, although you may not have labs scheduled in all sessions. Predominantly, these will take place in the MSc Laboratory. Precise details of activities and a laboratory timetable will be provided separately by the Programme Tutor and will also be available online at:
https://www.bris.ac.uk/eeng/intranet/pg/msc
Taught Phase
The assessment of this material is via a combination of continuous assessment (usually laboratory assignments) and formal examination.
Laboratory work
At various times throughout the year you will be asked to write about an aspect of your laboratory. Unless otherwise instructed, you will be asked to submit this either as a Technical Note (TN) or as a Full Report (FR). In either case the report should be written on an individual basis even if the lab was performed in groups.
A TN is briefer than an FR: you should refer to The Guidelines on Writing Technical Reports (Section 2.4) for more information on their structure and content.
As an approximate guide, we suggest that a TN should be 1000 words plus diagrams etc., whereas a FR should be 3000 words plus diagrams etc. Our time calculations are based on you spending (at most) 12 hours writing a TN and (at most) 24 hours writing a FR.
Where appropriate, your laboratory notebook will also be inspected from time to time by a member of staff or a demonstrator. Coursework or laboratory assessments will normally contribute 10-20% of the total unit assessment (see unit breakdown information on the MSc website for specific unit details): http://www.bris.ac.uk/eeng/intranet/units/programmes.html
Project phase assessment
Interim report assessment
The interim report will be independently assessed by both your supervisor and an assessor (these will be notified in advance). The assessment will be based on the following criteria:
Presentation and interview
Poster presentation
This will be performed by two members of staff who will undertake the assessment separately. They will first read through your poster and then ask you a number of questions relating to the work described. You will be given the opportunity to present any demonstrations you have prepared.
There are 12 branch libraries covering different disciplines and members of the University may use any of them. However, the Queen’s Building Library has the most relevant collections for the Electrical & Electronic Engineering students.
There are many information resources available to Electrical & Electronic Engineers. Library Services provides access to the most important ones via our resource gateway, MetaLib: http://metalib.bris.ac.uk
Barrass, R., Scientists Must Write, Science Paperbacks, 1978 Fitzroy Dearborn Publishers: editorial house style Kirkman, J., Good Style for Scientific and Engineering Writing, Pitman, 1992 University of Wales MSc. Student Handbook Van Emden, J., Handbook of Writing for Engineers, McMillan, 1990
