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Unit information: Design Verification in 2018/19

Please note: you are viewing unit and programme information for a past academic year. Please see the current academic year for up to date information.

Unit name Design Verification
Unit code COMS31700
Credit points 10
Level of study H/6
Teaching block(s) Teaching Block 1 (weeks 1 - 12)
Unit director Professor. Eder
Open unit status Not open
Pre-requisites

Programming Skills and Software Engineering Skills Knowledge of basic Computer Architecture

Co-requisites

None

School/department Department of Computer Science
Faculty Faculty of Engineering

Description

This unit introduces students to theoretical and practical aspects of design verification with a focus on HDL chip design. It starts with an overview of various verification techniques and explores their limits. We then focus on two major topics: Testing (dynamic verification) and Property Checking (static verification). Testing covers the use of simulators and assertions during simulation, building a test bench, collecting and measuring coverage. Property Checking investigates formal property specification languages, property checking techniques and how to obtain properties from a specification. The course concludes with lectures on design and verification flow, including how to devise an appropriate verification strategy, how to write a verification plan and how to decide when a design can be signed off.

Unit Aim: This unit familiarises students with the methods and techniques used in the design verification process, and gives them the technical background plus some of the practical skills expected from a design verification engineer.

Intended learning outcomes

On successful completion of this unit, students will be able to:

  • understand the process of design verification, its complexities and limits;
  • carry out functional verification and determine its effectiveness;
  • set verification goals and select suitable verification methods and techniques to achieve these;
  • compile a verification plan;
  • organise resources to be used for a verification project.

Teaching details

(interactive) lectures, hands-on demonstration sessions and laboratory exercises

Assessment Details

50% Coursework, 50% Written Examination

The coursework provides the students with an opportunity to undertake a small verification project. It requires the application of verification techniques in practice, including writing a verification plan, organization of resources, carrying out the verification and determining when the verification goals have been achieved.

The coursework is undertaken using state-of-the-art industrial verification tools.

This covers the learning outcomes as indicated by [x] below:

On successful completion of this unit, students will be able to: - understand the process of design verification, its complexities and limits;

  • carry out functional verification and determine its effectiveness;
  • set verification goals and select suitable verification methods and techniques to achieve these;
  • compile a verification plan;
  • organise resources to be used for a verification project.

Reading and References

J. Bergeron. Writing Testbenches: Functional Verification of HDL Models. Kluwer Academic Publishers, 2nd edition, 2003.

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