Unit name | Digital Design, Group Project |
---|---|
Unit code | EENG28010 |
Credit points | 10 |
Level of study | I/5 |
Teaching block(s) |
Teaching Block 2 (weeks 13 - 24) |
Unit director | Dr. Shuangyi Yan |
Open unit status | Not open |
Pre-requisites | |
Co-requisites |
none |
School/department | School of Electrical, Electronic and Mechanical Engineering |
Faculty | Faculty of Engineering |
The aim of this unit is to give students a practical introduction to digital logic design and prototyping in FPGAs based on VHDL entry, using industry standard tools. Students will work in groups to design a functioning digital system and implement it.
Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions, problem sheets and self-directed exercises.
Summative:
Assignment 1 : An individual take-home exercise that is assessed based on functionality and quality of VHDL code, and analytical and descriptive answers, all related to design of digital circuits and systems. (ILOs 1-6) Marked on a Pass/Fail basis
Assignment 2 : A group exercise that is assessed based on the functionality and quality of submitted code to meet specifications (ILOs 1-8). Marked on a Pass/Fail basis
Douglas L Perry, VHDL : Programming by Example, 4th Edition, McGraw-Hill 2002.
Volnei Pedroni Circuit Design with VHDL, MIT Press, 2004
J. Bhasker, A VHDL Synthesis Primer, 2nd ed, Star Galaxy Pub., 1998.