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Unit information: VLSI Design M in 2019/20

Please note: Due to alternative arrangements for teaching and assessment in place from 18 March 2020 to mitigate against the restrictions in place due to COVID-19, information shown for 2019/20 may not always be accurate.

Please note: you are viewing unit and programme information for a past academic year. Please see the current academic year for up to date information.

Unit name VLSI Design M
Unit code EENGM4050
Credit points 10
Level of study M/7
Teaching block(s) Teaching Block 2 (weeks 13 - 24)
Unit director Mr. Scott Tancock
Open unit status Not open

EENG20400 or equivalent



School/department Department of Electrical & Electronic Engineering
Faculty Faculty of Engineering


This unit introduces students to the principles of digital chip design.

Starting from a functional model of a MOSFET, analysis and design considerations for transistor level implementations of basic logic gates for different digital logic families are covered. These include static and dynamic logic styles for both combinational and sequential circuits.

Principles of synchronous system design are covered in detail, as are design techniques for dealing with signal integrity issues, and high performance and low power requirements.

The students will make extensive use of industry standard CAD tools for integrated circuit design, simulation and layout and gain experience in the design process from schematic entry to final tape-out of the chip.

Intended learning outcomes

Having completed this unit, students will be able to:

  1. Analyse digital logic circuits for functionality, performance, energy and power consumption
  2. Design MOSFET circuits to implement a given digital logic function in complementary and pass-transistor design styles
  3. Design and optimise digital MOSFET circuits to meet functional and performance constraints
  4. Construct the physical layout of small-scale circuits
  5. Describe synchronous design principles and apply them in system analysis
  6. Describe techniques for dealing with interconnect

Teaching details

Combination of lectures and laboratory sessions

Assessment Details

30% Set of design exercises using Cadence in the laboratory, plus analysis tasks, to be submitted along with a report (ILOs 1-4)

10% Mini project (ILO 3)

60% - Exam on lecture material, 2 hours, (ILOs 1-3, 5-6)

Reading and References

Rabaey, Chandrakasan and Nikolic, Digital Integrated Circuits, 2nd ed, ISBN10: 0130909963
Weste and Harris, CMOS VLSI Design, 4th ed, ISBN10:0-321-54774-8