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Unit information: Digital Design, Group Project in 2023/24

Please note: It is possible that the information shown for future academic years may change due to developments in the relevant academic field. Optional unit availability varies depending on both staffing, student choice and timetabling constraints.

Unit name Digital Design, Group Project
Unit code EENG28010
Credit points 10
Level of study I/5
Teaching block(s) Teaching Block 2 (weeks 13 - 24)
Unit director Dr. Shuangyi Yan
Open unit status Not open

EENG14000, EENG20400



School/department Department of Electrical & Electronic Engineering
Faculty Faculty of Engineering


The aim of this unit is to give students a practical introduction to digital logic design and prototyping in FPGAs based on VHDL entry, using industry standard tools. Students will work in groups to design a functioning digital system and implement it.

Intended learning outcomes

  1. Demonstrate, through practice, the use of VHDL as a modelling language to describe digital logic, including use of common templates to describe combinational and sequential logic blocks;
  2. Explain the hardware implications of a given piece of VHDL code and the limitations imposed in coding for synthesis;
  3. Design combinational and sequential logic blocks and finite-state machines in VHDL based on a given set of functional specifications;
  4. Interpret a specification for a digital system;
  5. Propose modular structural divisions for a complex digital system, and define interfaces for the constituent modules;
  6. Set-up and run simulations and debug VHDL code for correct functionality in the ModelSim simulator, and approach the testing and simulation of a design in a systematic manner;
  7. Use Xilinx to prototype designs in FPGAs;
  8. Familiarity with good practice in design management and effective collaboration in a shared group project.

Teaching details

Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions, problem sheets and self-directed exercises.

Assessment Details


Assignment 1 : An individual take-home exercise that is assessed based on functionality and quality of VHDL code, and analytical and descriptive answers, all related to design of digital circuits and systems. (ILOs 1-6) Marked on a Pass/Fail basis

Assignment 2 : A group exercise that is assessed based on the functionality and quality of submitted code to meet specifications (ILOs 1-8). Marked on a Pass/Fail basis


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