As part of ENPOWER we are organising the EEHCO workhops on the topic of energy proportional computing associated with HIPEAC. Follow the workshop links on the left to learn more about this.

A Special Issue on Energy Efficient Computing with Adaptive and Heterogeneous Architectures has now been published in IETCDT and it is available online at http://digital-library.theiet.org/content/journals/iet-cdt/9/1#headline1 

Nunez-Yanez, J, ‘Computing to the limit with heterogeneous CPU-FPGA devices in a video fusion application’. in: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag, pp. 41-53, 2016 (BEST PAPER AWARD)

J. Luis Nunez-Yanez, M. Hosseinabady and A. Beldachi, "Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling," in IEEE Transactions on Computers, vol. 65, no. 5, pp. 1484-1493, May 1 2016.,doi: 10.1109/TC.2015.2435771

Hosseinabady, M.; Nunez-Yanez, J.L., "Energy optimization of FPGA-based stream-oriented computing with power gating," in Field Programmable Logic and Applications (FPL), 2015 25th International Conference on , vol., no., pp.1-6, 2-4 Sept. 2015
doi: 10.1109/FPL.2015.7293946

Hosseinabady, M.; Nunez-Yanez, J.L., "Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices," in Field Programmable Logic and Applications (FPL), 2015 25th International Conference on , vol., no., pp.1-6, 2-4 Sept. 2015
doi: 10.1109/FPL.2015.7294016

Angeles Navarro, Rafael Asenjo, Andrés Rodríguez, J. Nunez-Yanez
Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB,
International Symposium on Parallel Computing with FPGAs, ParaFPGA 2015. 
Edinburgh, UK, 1 September, 2015

Nunez-Yanez, J., "Adaptive Voltage Scaling with in-situ Detectors in Commercial FPGAs," in Computers, IEEE Transactions on , vol.64, no.1, pp.45-53, Jan. 1 2015 doi: 10.1109/TC.2014.2365963

Nunez-Yanez, J. 2013. Energy proportional computing in commercial FPGAs with adaptive voltage scaling (PDF, 601kB). In Proceedings of the Tenth FPGAworld Conference (FPGAworld '13). ACM, New York, NY, USA, Article 6, 5 pages. DOI=10.1145/2513683.2513689.

Beldachi, Arash Farhadi; Nunez-Yanez, Jose L.: 'Run-time power and performance scaling in 28 nm FPGAs (PDF, 1,684kB)', IET Computers & Digital Techniques, 2014, DOI: 10.1049/iet-cdt.2013.0117

Nunez-Yanez, J., "Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling (PDF, 882kB)", HEART (Highly Efficient Accelerators and Reconfigurable Technology), Sendai, Japan, June, 2014

Nunez-Yanez, J, Beldachi, Arash Farhadi "Run-time power and performance scaling with CPU-FPGA hybrids (PDF, 620kB)",  NASA/ESA Adaptive Hardware and Systems conference, Leicester, UK, July 2014. ( Obtained the conference Best Paper Award)

Peng Sun, Jose Nunez-Yanez, Optimizing Memory Power in Hybrid ARM-FPGA Chips With Lossless Data Compressio (PDF, 410kB)n, FPGAWorld, Sweeden, September, 2014

Mohammad Hosseinabady and Jose Luis Nunez-Yanez, Run-Time Power Gating in Hybrid ARM-FPGA Devices (PDF, 679kB), Field Programmable Logic (FPL) 2014, Munich, September 2-4th, 2014

Arash beldachi and Jose Luis Nunez-Yanez, Accurate Power control and monitoring in ZYNQ boards (PDF, 312kB),  Field Programmable Logic (FPL) 2014, Munich, September 2-4th, 2014