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Unit name |
Digital Design, Group Project |
Unit code |
EENG28010 |
Credit points |
10 |
Level of study |
I/5
|
Teaching block(s) |
Teaching Block 2 (weeks 13 - 24)
|
Unit director |
Professor. Dinesh Pamunuwa |
Open unit status |
Not open |
Pre-requisites |
EENG14000, EENG20400
|
Co-requisites |
none
|
School/department |
School of Electrical, Electronic and Mechanical Engineering |
Faculty |
Faculty of Engineering |
Description including Unit Aims
The aim of this unit is to give students a practical introduction to digital logic design and prototyping in FPGAs based on VHDL entry, using industry standard tools. Students will work in groups to design a functioning digital system and implement it.
Intended Learning Outcomes
- Demonstrate, through practice, the use of VHDL as a modelling language to describe digital logic, including use of common templates to describe combinational and sequential logic blocks;
- Explain the hardware implications of a given piece of VHDL code and the limitations imposed in coding for synthesis;
- Design combinational and sequential logic blocks and finite-state machines in VHDL based on a given set of functional specifications;
- Interpret a specification for a digital system;
- Propose modular structural divisions for a complex digital system, and define interfaces for the constituent modules;
- Set-up and run simulations and debug VHDL code for correct functionality in the ModelSim simulator, and approach the testing and simulation of a design in a systematic manner;
- Use Xilinx to prototype designs in FPGAs;
- Familiarity with good practice in design management and effective collaboration in a shared group project.
Teaching Information
Laboratory classes, self-learning from reading course notes, examples of designs and provided code and text books.
Assessment Information
- Assignment 1 (35%): An individual take-home exercise that is assessed based on functionality and quality of VHDL code, and analytical and descriptive answers, all related to design of digital circuits and systems. (ILOs 1-6)
- Assignment 2 (60%): A group exercise that is assessed based on the functionality and quality of submitted code to meet specifications (ILOs 1-8).
- Peer assessment (5%): of the assessment is based on the performance of the individual as viewed by their group mates and the instructors. (ILO 8)
Reading and References
Douglas L Perry, VHDL : Programming by Example, 4th Edition, McGraw-Hill 2002.
Volnei Pedroni Circuit Design with VHDL, MIT Press, 2004
J. Bhasker, A VHDL Synthesis Primer, 2nd ed, Star Galaxy Pub., 1998.